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NCV4269A 5.0 V Micropower 150 mA LDO Linear Regulator with DELAY, Adjustable RESET, and Sense Output
The NCV4269A is a 5.0 V precision micropower voltage regulator with an output current capability of 150 mA. The output voltage is accurate within 2.0% with a maximum dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature drawing only 240 mA with a 1.0 mA load. This part is ideal for any and all battery operated microprocessor equipment. Microprocessor control logic includes an active reset output RO with delay and a SI/SO monitor which can be used to provide an early warning signal to the microprocessor of a potential impending reset signal. The use of the SI/SO monitor allows the microprocessor to finish any signal processing before the reset shuts the microprocessor down. The active Reset circuit operates correctly at an output voltage as low as 1.0 V. The Reset function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to the RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.
Features http://onsemi.com MARKING DIAGRAMS
8 8 1 SO-8 D SUFFIX CASE 751 1 8 8 1 SO-8 EXPOSED PAD PD SUFFIX CASE 751AC 1 14 14 1 SO-14 D SUFFIX CASE 751A 1 20 20 1 SO-20 DW SUFFIX CASE 751D 1 A WL, L YY, Y WW, W G, G = Assembly Location = Wafer Lot = Year = Work Week = Pb Free NCV4269A5 AWLYYWWG NCV4269A5G AWLYWW 4269A5 ALYW G 4269A5 ALYW G
* * * * * *
* * * * * * *
5.0 V 2.0% Output Low 240 mA Quiescent Current Active Reset Output Low Down to VQ = 1.0 V Adjustable Reset Threshold 150 mA Output Current Capability Fault Protection +60 V Peak Transient Voltage -40 V Reverse Voltage Short Circuit Thermal Overload Early Warning through SI/SO Leads Internally Fused Leads in SO-14 and SO-20 Packages Integrated Pullup Resistor at Logic Outputs (To Use External Resistors, Select the NCV4279A) Very Low Dropout Voltage Electrical Parameters Guaranteed Over Entire Temperature Range NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb-Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 1
1
Publication Order Number: NCV4269A/D
NCV4269A
I Reference and Trim Error Amplifier Q Current and Saturation Control RSO RRO
D or
RO
Reference
SO + - GND
RADJ SI
Figure 1. Block Diagram
PIN CONNECTIONS
1 8 RADJ D GND GND GND GND RO 1 14 SI I GND GND GND Q SO RADJ D NC GND GND GND GND NC NC RO
1
I SI RADJ D
Q SO RO GND
20 SI I NC GND GND GND GND NC Q SO SO-20L
SO-8
SO-14
PACKAGE PIN DESCRIPTION
Package Pin Number SO-8 3 4 5 - 6 7 8 1 2 - SO-8 EP 3 4 5 - 6 7 8 1 2 EPAD SO-14 1 2 3, 4, 5, 6, 10, 11, 12 - 7 8 9 13 14 - SO-20L 1 2 4, 5, 6, 7, 14, 15, 16, 17 3, 8, 9, 13, 18 10 11 12 19 20 - Pin Symbol RADJ D GND NC RO SO Q I SI EPAD
Function Reset Threshold Adjust; if not used to connect to GND. Reset Delay; To Set Time Delay, Connect to GND with Capacitor Ground No connection to these pins from the IC. Reset Output; The Open-Collector Output has a 20 kW Pullup Resistor to Q. Leave Open if Not Used. Sense Output; This Open-Collector Output is Internally Pulled Up by 20 kW pullup resistor to Q. If not used, keep open. 5 V Output; Connect to GND with a 10 mF Capacitor, ESR < 10 W. Input; Connect to GND Directly at the IC with a Ceramic Capacitor. Sense Input; If not used, Connect to Q. Connect to ground potential or leave unconnected
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NCV4269A
MAXIMUM RATINGS (TJ = -40C to 150C)
Parameter Input to Regulator Input Transient to Regulator Sense Input Reset Threshold Adjust Reset Delay Ground Reset Output Sense Output Regulated Output Junction Temperature Storage Temperature Input Voltage Operating Range Junction Temperature Operating Range LEAD TEMPERATURE SOLDERING AND MSL Parameter MSL, 20-Lead LS Temperature 265C Peak (Note 3) MSL, 8-Lead, 14-Lead, LS Temperature 265C Peak (Note 3) MSL, 8-Lead EP, LS Temperature 260C Symbol MSL MSL MSL Value 3 1 2 Symbol VI II VI VSI ISI VRADJ IRADJ VD ID Iq VRO IRO VSO ISO VQ IQ TJ TSTG VI TJ Min -40 Internally Limited - -40 -1 -0.3 -10 -0.3 Internally Limited 50 -0.3 Internally Limited -0.3 Internally Limited -0.5 -10 - -50 - -40 Max 45 Internally Limited 60 45 1 7 10 7 Internally Limited - 7 Internally Limited 7 Internally Limited 7.0 - 150 150 45 150 Unit V V V mA V mA V mA V V V mA C C V C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and exceeds the following ratings: Human Body Model (HBM) 4.0 kV per AEC-Q100-002. Machine Model (MM) 200 V per AEC-Q100-003. 2. Latchup Current Maximum Rating: 150 mA per AEC-Q100-004. 3. +5C/-0C, 40 Sec Max-at-Peak, 60 - 150 Sec above 217C.
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NCV4269A
THERMAL CHARACTERISTICS
Characteristic SO-8 Package (Note 4) Junction-to-Pin 4 ( Y - JL4, YL4) Junction-to-Ambient Thermal Resistance (RqJA, qJA) SO-8 EP Package (Note 4) Junction-to-Pin 8 ( Y - JL8, YL8) Junction-to-Ambient Thermal Resistance (RqJA, qJA) Junction-to-Pad ( Y - JPad) SO-14 Package (Note 4) Junction-to-Pin 4 ( Y - JL4, YL4) Junction-to-Ambient Thermal Resistance (RqJA, qJA) SO-20 Package (Note 4) Junction-to-Pin 4 ( Y - JL4, YL4) Junction-to-Ambient Thermal Resistance (RqJA, qJA) 4. 2 oz copper, 50 mm2 copper area, 1.5 mm thick FR4 21.8 95.3 C/W C/W 18.4 111.6 C/W C/W 23.7 71.4 7.7 C/W C/W C/W 53.8 170.9 C/W C/W Test Conditions (Typical Values) Unit
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NCV4269A
ELECTRICAL CHARACTERISTICS (TJ = -40C TJ 125C, VI = 13.5 V unless otherwise specified)
Characteristic REGULATOR Output Voltage Current Limit Current Consumption; Iq = II - IQ Current Consumption; Iq = II - IQ Current Consumption; Iq = II - IQ Dropout Voltage Load Regulation Line Regulation RESET GENERATOR Reset Switching Threshold Reset Adjust Switching Threshold Reset Pullup Resistance Reset Output Saturation Voltage Upper Delay Switching Threshold Lower Delay Switching Threshold Saturation Voltage on Delay Capacitor Charge Current Delay Time L H Delay Time H L INPUT VOLTAGE SENSE Sense Threshold High Sense Threshold Low Sense Output Saturation Voltage Sense Resistor Pullup Sense Input Current VSI,High VSI,Low VSO,Low RSO,INT ISI - - VSI < 1.20 V; VQ > 3 V; RSO - - 1.24 1.16 - 10 -1.0 1.31 1.20 0.1 20 0.1 1.38 1.28 0.4 40 1.0 V V V kW mA VRT VRADJ,TH RSO,INT VRO,SAT VUD VLD VD,SAT ID,C td tRR - VQ > 3.5 V - VQ < VRT, RRO, INT - - VQ < VRT VD = 1 V CD = 100 nF CD = 100 nF 4.50 1.26 10 - 1.4 0.3 - 3.0 17 - 4.65 1.35 20 0.1 1.8 0.45 - 6.5 28 3.15 4.80 1.44 40 0.4 2.2 0.60 0.1 9.5 - - V V kW V V V V mA ms ms VQ IQ Iq Iq Iq Vdr DVQ DVQ 1 mA v IQ v 100 mA 6 V v VI v 16 V - IQ = 1 mA, RO, SO High IQ = 10 mA, RO, SO High IQ = 50 mA, RO, SO High VI = 5 V, IQ = 100 mA IQ = 5 mA to 100 mA VI = 6 V to 26 V IQ = 1 mA 4.90 150 - - - - - - 5.00 200 190 250 2.0 0.25 10 10 5.10 500 250 450 3.0 0.5 20 30 V mA mA mA mA V mV mV Symbol Test Conditions Min Typ Max Unit
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NCV4269A
II IQ
I CI 470 nF ISI SI D
Q
1000 mF
RADJ1 RADJ SO IRADJ
CQ 22 mF VQ
VI
GND
RO
VSI
ID
Iq
VRO
VSO
VRADJ
CD 100 nF
VD
RADJ2
Figure 2. Measuring Circuit
VI
t VQ VRT t VD VUD VLD td VRO VRO,SAT tRR t dV I +D dt CD < tRR
t Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
Power-on-Reset
Figure 3. Reset Timing Diagram
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NCV4269A
Sense Input Voltage
VSI,High
VSI,Low
t Sense Output Voltage
High
Low
t
Figure 4. Sense Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
16 14 12 ID,C, (mA) 10 8 6 4 2 0 -40 0 40 TJ, (C) 80 120 160 VD, (V) VI = 13.5 V VD = 1.0 V 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 -40 0 40 TJ, (C) 80 120 160 VLD VUD VI = 13.5 V
Figure 5. Charge Current ID,C vs. Temperature TJ
Figure 6. Switching Voltage VUD and VLD vs. Temperature TJ
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NCV4269A
TYPICAL PERFORMANCE CHARACTERISTICS
500 400 VRAD,JTH, (V) TJ = 125C Vdr, (mV) 300 200 TJ = -40C 100 0 0 TJ = 25C 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 30 60 90 IQ, (mA) 120 150 180 0.9 -40 0 40 TJ, (C) 80 120 160
Figure 7. Drop Voltage Vdr vs. Output Current IQ
35 30 25 Iq, (mA) VQ (V) 20 15 10 5 0 0 10 RL = 50 W RL = 33 W 12 10 8 6 4 2 30 VI, (V) 40 50 0 0
Figure 8. Reset Adjust Switching Threshold, VRADJ,TH vs. Temperature TJ
RL = 50 W
RL = 100 W
RL = 200 W
20
2
4 VI, (V)
6
8
10
Figure 9. Current Consumption Iq vs. Input Voltage VI
Figure 10. Output Voltage VQ vs. Input Voltage VI
1.6 1.5 1.4 VSI, (V) 1.3 1.2 1.1 1.0 -40 VI = 13.5 V
5.2 5.1 VSI, High VQ, (V) VSI, Low 5.0 4.9 4.8 4.7 0 40 TJ, (C) 80 120 160 4.6 -40 0 40 TJ, (C) 80 120 160 VI = 13.5 V
Figure 11. Sense Threshold VSI vs. Temperature TJ
Figure 12. Output Voltage VQ vs. Temperature TJ
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NCV4269A
TYPICAL PERFORMANCE CHARACTERISTICS
350 300 250 IQ, (mA) 200 150 100 50 0 0 10 20 VI, (V) 30 40 50 TJ = 25C Iq, (mA) 12 10 8 6 4 2 0 0 VI = 13.5 V TJ = 25C
TJ = 125C
20
40
60 IQ, (mA)
80
100
120
Figure 13. Output Current Limit IQ vs. Input Voltage VI
1.6 1.4 1.2 1.0 Iq, (mA) 0.8 0.6 0.4 0.2 0.0 0 10 20 IQ, (mA) 30 40 50 Iq, (mA) VI = 13.5 V TJ = 25C 7 6 5 4 3 2 1 0 6
Figure 14. Current Consumption Iq vs. Output Current IQ
TJ = 125C IQ = 100 mA
IQ = 50 mA IQ = 10 mA 8 10 12 14 16 VI, (V) 18 20 22 24 26
Figure 15. Current Consumption Iq vs. Output Current IQ
250 TJ = 25C 200 10 Iq, (mA) 150 IQ = 100 mA ESR (W) 100
Figure 16. Quiescent Current Iq vs. Input Voltage VI
Unstable Region
1 100
Stable Region for 2.2 mF to 10 mF
50 6
8
10
12
14
16 VI, (V)
18
20
22
24
26
0.1 0
25
50
75
100
125
150
OUTPUT CURRENT IN MILLIAMPS
Figure 17. Quiescent Current Iq vs. Input Voltage VI
Figure 18. Output Stability, Capacitance ESR vs. Output Load Current
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NCV4269A
TYPICAL THERMAL CHARACTERISTICS
200 180 160 140 qJA (C/W) 120 100 80 60 40 20 0 0 100 200 300 400 500 600 700
COPPER HEAT-SPREADER AREA (mm2) SO-8 Std Package NCV4269A, 1.0 oz SO-8 Std Package NCV4269A, 2.0 oz SO-14 w/6 Thermal Leads NCV4269A, 1.0 oz SO-14 w/6 Thermal Leads NCV4269A, 2.0 oz SO-20 w/8 Thermal Leads NCV4269A, 1.0 oz SO-20 w/8 Thermal Leads NCV4269A, 2.0 oz
Figure 19. Junction-to-Ambient Thermal Resistance (qJA) vs. Heat Spreader Area
1000
100
R(t) (C/W)
10
1
0.1 0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (s) Single Pulse (SO-8 Std Package) PCB = 50 mm2, 2.0 oz Single Pulse (SO-8 EP Package) Single Pulse (SO-14 w/6 Thermal Leads) PCB = 50 mm2, 2.0 oz Single Pulse (SO-20 w/8 Thermal Leads) PCB = 50 mm2, 2.0 oz YLA (SO-8) YLA (SO-14) YLA (SO-20)
Figure 20. R(t) vs. Pulse Time
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NCV4269A
APPLICATION DESCRIPTION
OUTPUT REGULATOR
The output is controlled by a precision trimmed reference. The PNP output has base drive quiescent current control for regulation while the input voltage is low, preventing over saturation. Current limit and voltage monitors complement the regulator design to give safe operating signals to the processor and control circuits.
RESET OUTPUT (RO)
If the reset adjust option is not needed, the RADJ pin should be connected to GND causing the reset threshold to go to its default value (typically 4.65 V).
RESET DELAY (D)
A reset signal, Reset Output, RO, (low voltage) is generated as the IC powers up. After the output voltage VQ increases above the reset threshold voltage VRT, the delay timer D is started. When the voltage on the delay timer VD passes VUD, the reset signal RO goes high. A discharge of the delay timer VD is started when VQ drops and stays below the reset threshold voltage VRT. When the voltage of the delay timer VD drops below the lower threshold voltage VLD the reset output voltage VRO is brought low to reset the processor. The reset output RO is an open collector NPN transistor with an internal 20 kW pullup resistor connected to the output Q, controlled by a low voltage detection circuit. The circuit is functionally independent of the rest of the IC, thereby guaranteeing that RO is valid for VQ as low as 1.0 V. The reset threshold VRT can be decreased from a typical value of 4.65 V to as low as 3.5 V by using an external voltage divider connected from the Q lead to the pin RADJ, as shown in Figure 21. The resistor divider keeps the voltage above the VRADJ,TH (typical 1.35 V) for the desired input voltages, and overrides the internal threshold detector. Adjust the voltage divider according to the following relationship:
VRT + VRADJ, TH @ (RADJ1 ) RADJ2) RADJ2 VBAT CI* 0.1 mF (eq. 1)
The reset delay circuit provides a delay (programmable by capacitor CD) on the reset output lead RO. The delay lead D provides charge current ID,C (typically 6.5 mA) to the external delay capacitor CD during the following times: 1. During Powerup (once the regulation threshold has been exceeded). 2. After a reset event has occurred and the device is back in regulation. The delay capacitor is set to discharge when the regulation (VRT, reset threshold voltage) has been violated. When the delay capacitor discharges to VLD, the reset signal RO pulls low.
SETTING THE DELAY TIME
The delay time is set by the delay capacitor CD and the charge current ID. The time is measured by the delay capacitor voltage charging from the low level of VDSAT to the higher level VUD. The time delay follows the equation:
td + [CD (VUD * VD, SAT)] ID, C (eq. 2)
RESET ADJUST (RADJ)
Example: Using CD = 100 nF. Use the typical value for VD,SAT = 0.1 V. Use the typical value for VUD = 1.8 V. Use the typical value for Delay Charge Current ID = 6.5 mA.
td + [100 nF (1.8 * 0.1 V)] 6.5 mA + 26.2 ms (eq. 3)
I
Q RADJ1 RADJ CQ** 10 mF (2.2 mF) RSI1
VDD
NCV4269A
D CD SI
RADJ2
RSI2
SO
RO GND
I/O
*CI required if regulator is located far from the power supply filter. ** CQ - minimum cap required for stability is 2.2 mF while higher over/under-shoots may be expected. Cap must operate at minimum temperature expected.
Figure 21. Application Diagram http://onsemi.com
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Microprocessor
I/O
NCV4269A
SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGE MONITOR
An on-chip comparator is available to provide early warning to the microprocessor of a possible reset signal (Figure 4). The output is from an open collector driver with an internal 20 kW pull up resistor to output Q. The reset signal typically turns the microprocessor off instantaneously. This can cause unpredictable results with the microprocessor. The signal received from the SO pin will allow the microprocessor time to complete its present task before shutting down. This function is performed by a comparator referenced to the band gap voltage. The actual trip point can be programmed externally using a resistor divider to the input monitor SI (Figure 21). The values for RSI1 and RSI2 are selected for a typical threshold of 1.20 V on the SI Pin.
SIGNAL OUTPUT
(-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The 10 mF output capacitor CQ shown in Figure 21 should work for most applications; however, it is not necessarily the optimized solution. Stability is guaranteed at CQ is min 2.2 mF and max ESR is 10 W. There is no min ESR limit which was proved with MURATA's ceramic caps GRM31MR71A225KA01 (2.2 mF, 10 V, X7R, 1206) and GRM31CR71A106KA01 (10 mF, 10 V, X7R, 1206) directly soldered between output and ground pins.
CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output regulator (Figure 21) is:
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max) Iq (eq. 4)
Figure 22 shows the SO Monitor timing waveforms as a result of the circuit depicted in Figure 21. As the output voltage (VQ) falls, the monitor threshold (VSI,Low), is crossed. This causes the voltage on the SO output to go low sending a warning signal to the microprocessor that a reset signal may occur in a short period of time. TWARNING is the time the microprocessor has to complete the function it is currently working on and get ready for the reset shutdown signal. When the voltage on the SO goes low and the RO stays high the current consumption is typically 560 mA at 1 mA load current.
VQ
where: VI(max) is the maximum input voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, and Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
RqJA = (150C - TA) / PD (eq. 5)
SI VSI,Low
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. The current flow and voltages are shown in the Measurement Circuit Diagram.
HEATSINKS
VRO
SO
TWARNING
Figure 22. SO Warning Waveform Time Diagram STABILITY CONSIDERATIONS
A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA (eq. 6)
The input capacitor CI in Figure 21 is necessary for compensating input line reactance. Possible oscillations caused by input inductance and input capacitance can be damped by using a resistor of approximately 1.0 W in series with CI. The output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heat sink thermal resistance, and RqSA = the heat sink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D, available on the ON Semiconductor website.
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NCV4269A
ORDERING INFORMATION
Device NCV4269AD150G NCV4269AD150R2G NCV4269APD50G NCV4269APD50R2G NCV4269AD250G NCV4269AD250R2G NCV4269ADW50G NCV4269ADW50R2G 5.0 V Output Voltage Package SO-8 (Pb-Free) SO-8 (Pb-Free) SO-8 EP (Pb-Free) SO-8 EP (Pb-Free) SO-14 (Pb-Free) SO-14 (Pb-Free) SO-20L (Pb-Free) SO-20L (Pb-Free) Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel 38 Units/Rail 1000 Tape & Reel
For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCV4269A
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X-
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV4269A
PACKAGE DIMENSIONS
SOIC-8 EP CASE 751AC-01 ISSUE B
2X
D A
8 5
0.10 C A-B D DETAIL A
EXPOSED PAD 5
F
8
E1
2X
E
2X 4
G h
4 1
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. DIM A A1 A2 b b1 c c1 D E E1 e L L1 F G h q MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_
0.10 C D
PIN ONE LOCATION
0.10 C
8X
A2
0.10 C
SEATING PLANE
GAUGE PLANE
b1 L (L1) DETAIL A q
C
SIDE VIEW
A1
0.25
c1
SECTION A-A
SOLDERING FOOTPRINT*
2.72 0.107 1.52 0.060
7.0 0.275
2.03 0.08
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CC EE CC EE CC EE
EEE EEE EEE
1
0.20 C
8X b 0.25 C A-B D
e
BOTTOM VIEW
B
A
A
END VIEW H c
TOP VIEW A
(b)
Exposed Pad
mm inches
NCV4269A
PACKAGE DIMENSIONS
SO-14 CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G
C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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NCV4269A
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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